-- $Id: $
-- File name:   tb_CLK_DIV.vhd
-- Created:     3/22/2011
-- Author:      Brandon Blaine Gardner
-- Lab Section: 337-06
-- Version:     1.0  Initial Test Bench

library ieee;
--library gold_lib;   --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
--use gold_lib.all;   --UNCOMMENT if you're using a GOLD model

entity tb_CLK_DIV is
generic (Period : Time := 5.2083 ns);
end tb_CLK_DIV;

architecture TEST of tb_CLK_DIV is

  function INT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
     return STD_LOGIC_VECTOR is
    variable RES : STD_LOGIC_VECTOR(NumBits-1 downto 0);
    variable tmp : INTEGER;
  begin
    tmp := X;
    for i in 0 to NumBits-1 loop
      if (tmp mod 2)=1 then
        res(i) := '1';
      else
        res(i) := '0';
      end if;
      tmp := tmp/2;
    end loop;
    return res;
  end;

  component CLK_DIV
    PORT(
         RST : in std_logic;
         CLK_in : in std_logic;
         CLK_48 : out std_logic;
         CLK_24 : out std_logic
    );
  end component;

-- Insert signals Declarations here
  signal RST : std_logic;
  signal CLK_in : std_logic;
  signal CLK_48 : std_logic;
  signal CLK_24 : std_logic;

-- signal <name> : <type>;

begin

CLKGEN: process
  variable CLK_in_tmp: std_logic := '0';
begin
  CLK_in_tmp := not CLK_in_tmp;
  CLK_in <= CLK_in_tmp;
  wait for Period/2;
end process;

  DUT: CLK_DIV port map(
                RST => RST,
                CLK_in => CLK_in,
                CLK_48 => CLK_48,
                CLK_24 => CLK_24
                );

--   GOLD: <GOLD_NAME> port map(<put mappings here>);

process

  begin

-- Insert TEST BENCH Code Here

    RST <= '0';
    
    wait for Period*2;
    
    RST <= '1';
    
    wait;

  end process;
end TEST;